1. Field of the Invention
The present invention relates to debugging a low power IC design and, in particular, to debugging of a low power IC design using power sequence checking rules.
2. Description of the Related Art
With the rapid progress of mobile devices and consumer electronic equipment in recent years, there are more and more sophisticated gadgets that are available to the public, such as smart cellular phones, personal mobile computers, MP3 audio players, notebooks and digital cameras. As additional functions and low power consumption are needed in thinner and lighter electronic products, IC designers wish to integrate varieties of discrete components on one chip to suit these requirements, which allows fewer components for a system design and smaller size of a printed circuit board (PCB). For example, system-on-chip (SoC) design becomes much more complex and harder to debug as more and more digital circuit and low power network designs are integrated into one chip. In many low power designs, a circuit design is divided into a multitude of parts and each part, called a power domain, has its own power supply. In other words, a power domain is a collection of instances, pins and ports that share the same power distribution network (voltage). Some of the power domains can be turned on or off by power switches. The objective of using a power switch is to turn off power supply to unused parts of the power domains to conserve power.
Referring to FIG. 1, a digital circuit design is conventionally implemented in hardware description language (HDL). HDL design files, HDL netlists, or HDL code can be simulated with test benches to verify their functionality. Verilog and VHDL are two commonly used HDLs. In the example shown in FIG. 1, a HDL netlist includes a module A having inputs clk, a, b, and output c. In addition to the HDL netlist, IC designers may separately describe the “power intent” (intended power behavior) aspect of the IC in a low power specification. There are two low power specifications: One is the Common Power Format (CPF) developed by Cadence Design Systems and managed by the Silicon Integration Initiative's (Si2's) Low Power Coalition. The other one is the Unified Power Format (UPF). These two CPF and UPF are herein referred to as xPF format, xPF file, or xPF specification. The xPF specification enables designers to specify design intents as power management information in a separate file without modifying the HDL code (Verilog or VHDL netlists). The xPF specification also provides other elements such as isolation cells, level shifter cells, and retention cells for power domains which are essential for proper functioning across power switching. The power format is just a format to describe low power intent for design implementation, analysis and verification, and it is not limited to the CPF or UPF as long as it serves the low power design purpose. An exemplary syntax of the xPF commands includes “create_power_domain_PD_FSM” and “set_isolation iso_PCU-domain,” as shown in FIG. 1.
Since traditional hardware description languages (HDL) are not adequate to specify the power design information, power formats, such as xPF files, provide a format without touching the existing HDL codes. For instance, xPF provides a command, create_power_domain, for creating a power domain and grouping design instances sharing the same power domain together. Other power components, such as power switches, isolation cells, and level shifters can be easily created by using the corresponding commands defined within the xPF files.
Once the HDL design and the power design based on the power format are taken into consideration, the entire IC design can be analyzed and a subsequent debugging simulation can be performed. Because HDL descriptions and xPF descriptions are in separate files, it is cumbersome for IC designers to detect and debug when there is an anomaly in signal behaviors. Moreover, both HDL and xPF are text descriptions, which make it even harder for designers to have a full picture in mind for detecting and debugging anomalies or errors between the IC design and power specification.
Therefore, what is needed is a systematic way to detect and debug errors in a lower power IC design to ensure that the entire IC design is correct.